


module divider_tb();

parameter WIDTH_N = 8;
parameter WIDTH_D = 4;
parameter LOG2_WIDTH_N = 3; //log2(WIDTH_N)

reg clk,rst,load;

reg [WIDTH_N-1:0] n;
reg [WIDTH_D-1:0] d;
wire [WIDTH_N-1:0] q_b;
wire [WIDTH_D-1:0] r_b;
wire ready_b;


/////////////////
// plain DUT
/////////////////
divider dvb(
            .clk(clk),
            .rst(rst),

            .load(load),
            .n(n),
            .d(d),

            .q(q_b),
            .r(r_b),
            .ready(ready_b)
            );

    defparam dvb.WIDTH_N = WIDTH_N;
    defparam dvb.WIDTH_D = WIDTH_D;
    defparam dvb.LOG2_WIDTH_N = LOG2_WIDTH_N;

/////////////////
// simple model
/////////////////
integer expected_q = 0, expected_r = 0;
always @(posedge clk or posedge rst) begin
    if (rst) begin
        expected_q <= 0;
        expected_r <= 0;
    end
    else begin
        if (load) begin
            expected_q <= n/d;
            expected_r <= n%d;
        end
    end
end

/////////////////
// start test
/////////////////
reg fail;
initial begin
    clk = 0;
    rst = 0;
    fail = 0;
    load = 0;
    #10 rst = 1;
    #10 rst = 0;
    #10000000 if (!fail) $display ("PASS"); else $display ("FAIL");
    $display ("%d correct answers",tests);
    $stop;
end


always begin
    #100 clk = ~clk;
end

////////////////////
// stim generation
////////////////////
integer tests = 0;
always @(posedge clk) begin
    #10
    if (!load & ready_b)
    begin
        @(negedge clk);
        load = 1;
        n = 31;//$random;
        d = 5;//$random;
        // don't divide by zero
        if (d == 0) d = 1;

        @(posedge clk);
        @(negedge clk);
        load = 0;
        tests = tests + 1;
    end
end

////////////////////
// answer checking
////////////////////

always @(posedge ready_b)
begin
    #10
    if (q_b != expected_q || r_b != expected_r) begin
            $display ("Mismatch on unit B at time %d : %d %d vs %d %d",
                $time,q_b,r_b,expected_q,expected_r);
        fail = 1;
    end
end

//Debussy Simulation Wave File
initial
begin
$fsdbDumpfile("wave.fsdb");
$fsdbDumpvars;
end

endmodule

